IBM debuts ‘world’s first’ sub-1 nanometer chip technology

IBM announced a new "sub-1 nanometer" chip architecture called nanostack that can integrate nearly 100 billion transistors on a fingernail-sized chip—double the density of its previous generation. The technology vertically stacks transistors in a staggered layout to achieve what IBM describes as 0.7-nanometer performance specifications, potentially delivering 50 percent higher computing performance or 70 percent greater energy efficiency than its 2-nanometer chips. IBM notes the "node" designation reflects performance metrics rather than actual physical dimensions, a standard industry practice for advanced chip generations.